Processing Instruction - PDFSEARCH.IO - Document Search Engine

Processing Instruction
Results: 1077

#	Item
41	XQuery 1.0: Primer by Juliane Harbarth, Technical Consultant R&D Technology, Software AG Abstract This document is intended to provide an easily readable description of the XQuery XML Query language, and is oriented towa Add to Reading List Source URL: web.archive.org Language: English Computing Query languages Functional languages 4GL XQuery Markup languages XPath FLWOR XML database Database Processing Instruction JSONiq
42	BOOKS ABOUT PAINSTRUCTIONS Cityhalllosangeles.com PAINSTRUCTIONS Add to Reading List Source URL: p.cityhalllosangeles.com Language: English - Date: 2015-03-05 01:51:59 Central processing unit Instruction set
43	This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and shar Add to Reading List Source URL: ccn.upenn.edu Language: English - Date: 2012-05-25 17:21:27 Semantics Cognitive science Neuroscience Cognition Analogy Priming Lateralization of brain function Artificial neural network Relation Semantic similarity Analogical models Semantic processing
44	MIPS Assembly Language Programmer’s Guide ASM-01-DOC Your comments on our products and publications Add to Reading List Source URL: www.tik.ee.ethz.ch Language: English - Date: 2009-09-02 12:08:50 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Assembly languages Programming language implementation Reduced instruction set computing IBM Basic assembly language and successors Processor register Instruction set Coprocessor
45	Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2016-02-24 05:00:01 Instruction set architectures Reduced instruction set computing RISC-V Instruction set ARM architecture Comparison of instruction set architectures
46	Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach 1 Abbas Rahimi CSE, UC San Diego La Jolla, CA 92093, USA Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2014-02-11 01:12:49 Parallel computing Central processing unit Computer architecture Instruction set architectures Instruction set SIMD Program counter ARM architecture Processor register General-purpose computing on graphics processing units OpenMP
47	CS:APP2e Guide to Y86 Processor Simulators∗ Write back Stat Add to Reading List Source URL: csapp.cs.cmu.edu Language: English - Date: 2013-07-29 12:14:16 Simulation software Central processing unit Computer architecture Assembly language Programming language implementation Instruction set simulator Register file Instruction set Pointer GNU Core Utilities
48	PLACES 22nd March 2009 Programming Language Approaches to Concurrency and Communication-cEntric Software is a workshop at ETAPS 2009, York, England Add to Reading List Source URL: places09.di.fc.ul.pt Language: English - Date: 2009-03-12 05:21:57 Concurrency control Parallel computing Concurrent computing Transaction processing Central processing unit Thread Monitor Software transactional memory Multi-core processor Lock Transactional memory Instruction set
49	Godson-2E software manual Contents 1 Godson-2E Micro Architecture...................................................................................1 1.1 Godson Series Processors ........................................ Add to Reading List Source URL: dev.lemote.com Language: English - Date: 2011-05-04 12:04:52 Central processing unit CPU cache Translation lookaside buffer Loongson Processor register Control register Instruction set Addressing mode MIPS instruction set Draft:Cache memory
50	Using Cortex-M3 and Cortex-M4 Fault Exception Application Note 209 Abstract The Cortex-M processors implement an efficient exception model that also traps illegal memory accesses and several incorrect program conditions. Add to Reading List Source URL: www.keil.com Language: English - Date: 2016-03-11 03:37:29 Computer errors Memory management Central processing unit Instruction set architectures ARM architecture Bus error Control register Page fault Segmentation fault Memory protection ARM Cortex-M Exception handling